A method of fabricating a semiconductor device in which trenches corresponding to a source region and a drain region, respectively, are formed in a Si substrate, a plurality of facets are provided on each of sidewall surfaces of the trenches thus formed, and a SiGe mixed crystal layer is epitaxially grown in each of the trenches each having a plurality of facets on a sidewall surface thereof to be filled therein is described as a conventional method of fabricating a semiconductor device in Japanese Patent KOKAI No. 2006-186240. According to the method of fabricating a semiconductor device described in Japanese Patent KOKAI No. 2006-186240, a plurality of facets are provided on each of the sidewall surfaces of the trenches, which results in that a compressive stress applied to a channel region can be optimized, thereby improving an operation speed of the semiconductor device.